Modular solid state power controller with microcontroller

ABSTRACT

An improved modular solid power controller includes low cost low speed microcomputers embedded within the load cards to control a number of semiconductor power switches associated with corresponding electrical load circuits. A master controller microcomputer on the controller card communicates bilaterally with each of such slave microcomputers via a serial data path that extends along the backplane card and interconnects the former computer with each of the load cards, issuing commands in serial form and in high level language that is received by the addressed slave microprocessor, interpreted and acted upon by controlling the semiconductor power switches associated with the respective slave card.

This application is a continuation of application Ser. No. 08/513,714,filed Aug. 11, 1995 now abandoned.

FIELD OF THE INVENTION

This invention relates to modular solid state computer controlled powercontrollers and, more particularly, to fault tolerant power controllersfor electrical power systems management systems for vehicles, such asair craft, space craft, and marine electrical systems, having multipleseparately controlled electrical loads.

BACKGROUND

Electrical power load management provides automation for control ofelectrical switches, energizes and de-energizes individual electricalloads, and provides fault isolation and wire protection in various kindsof vehicles, such as automobiles, aircraft, space craft and ships, bymeans of electrical load control units referred to herein as ElectricLoad Management Centers, "ELMC". Various numbers and sizes of ELMCs areplaced at various locations around the vehicle, typically, to optimizeoverall vehicle packaging and minimize power distribution qualityproblems, such as electromagnetic interference, "EMI", and minimize thevoltage drops that inherently occur along transmission lines andincrease with the transmission line's length. Apart from the physicalhousing for the unit, present ELMC's contain three basic electricalcharacteristics; individual power control devices such aselectromechanical relays, fuses and circuit breakers, the necessarycommand and data management to support such power control devices, andan interconnection system, such as a wiring harness or printed circuitboard.

The ELMC's power control devices require ELMC electrical interfaces forcommand and control signals, data acquisition for "health" monitoring ofthe equipment's operation and the power signals which areinterconnecting the electrical supply with the electrical load. Whenmany such power control devices are located in one ELMC, a problemarises in handling the number of electrical interfaces to the powercontrol devices. The command and data management system within the ELMCtypically contains a microprocessor, microcontroller, digital statemachine or analog controller, as variously termed and which is referredto herein as a "microcomputer", to provide the ability to manage themany control and data signals passing between other vehicle systems andthe individual power control devices.

Such management system, in addition, typically contains datamultiplexing circuits between the microcomputer and the many powercontrol devices. Such data multiplexing circuits are used to interfacethe parallel digital bus, originating from the microcomputer, with themany discrete electrical signals associated with the power controldevices. The electrical interconnection, such as a wiring harness orprinted circuit card, carries all the electrical signals, includingpower, control and data, that are routed between the ELMC's input andoutput electrical connectors and the many internal ELMC components.

The microcomputer serves as the ELMC's primary interface with thevehicle management system and communications with that system and isconnected to the system via an appropriate data bus. To the present, thearchitecture of such ELMC units employ a microcomputer and one or moredata multiplexing printed circuit cards, herein referred to simply as"cards", whereby discrete commands to the individual power controldevices are interfaced to the microcomputer's parallel digital bus port.This interfacing allows computer software, the program associated withthe microcomputer, to manage discrete command signals and datainterfacing with the many power control devices. In using a parallelform of data transmission between the microcomputer and the datamultiplexing cards, and then many discrete electrical command and datasignals interfacing with the power control devices, presumably thethinking of the designers of that system may have been that theinformation is thereby propagated more quickly and reliably than aserial bus arrangement and provides a method to interface with the manysignals associated with the power control devices.

Further, newer power management systems of the foregoing type proposeuse of solid state power controllers, herein referred to as "SSPC", asthe power control device. SSPCs are typically a collection of powerelectronics and associated analog control electronics placed into asingle electrical component package. One typical SSPC function is thatof overcurrent protection for the electrical load. The SSPC thereforeprovides a solid state electronic alternative to the fuse, relay andcircuit breaker used in the earlier prior art.

To carry out its function therein, each SSPC switch requires a number ofdiscrete I/O signals, that is, command signals, which are low power TTLlevel interconnects between high impedance sources and sinks. These lowpower command signals are of necessity placed in close proximity to thehigh current power supply conductors and load conductors on theinterconnecting backplane card, which interconnects the same SSPCswitches to the microcomputer. Without taking extraordinary protection,the low level discrete signal lines in the backplane can be perturbed bythe electromagnetic radiation interference, EMI, radiated from the highcurrent source and the load conductors that share the space on thebackplane. With ELMC's containing ever more greater number of SSPCcards, that EMI problem is exacerbated.

Prior design practice was to decode the system data bus command on themicrocomputer card, and then issue discrete commands, typically TTLlevel signals, via the backplane and the data multiplexing card (I/O) tothe individual SSPC. Likewise, data from the SSPC was transmitted backto the microcomputer card, via the backplane and the I/O card for actionby the microcomputer or for presentation to the system data bus. Thelatter data was also typically TTL level signals and low level analogsignals, typically in the range of 0 to 5.0 volts. In total, the commandand data interface signals required between eight and ten backplaneconductors, "traces", each for each power control switch. For an averageSSPC population of 100 switches, as example, the backplane is requiredto support up to 1,000 low level signals, requiring that many tracelines and plated vias.

Those 1,000 lines extend lengthwise down the backplane and were orientedfor most of that length in parallel to the high power source and loadconductors. Unfortunately that parallel orientation is precisely optimalfor electromagnetic coupling of energy from the power conductors to thelow level signal conductors. To prevent corruption of the low levelsignal, thus, special precautions must be taken, which undesirably addsto the parts count, power consumption, weight and size of the ELMC. Evenhaving taken such precautions, signal corruption may still occur,leading to system malfunctions and the return of questionable data tothe vehicle management system.

Further, as greater number of processing functions are demanded of themicroprocessor in such systems for completion within a prescribed shorttime interval, faster microprocessors must be substituted. It isestimated that the microprocessor in present ELMC systems must minimallyaccomplish a through-put of one mip. Moreover, if special dataprocessing is required, such as the processing required for arcdetection and fault diagnostics, a minimum through-put of fifteen mipsis required. With faster microprocessors there is greater heatproduction, an undesirable side effect in most vehicle systems; andthose faster microprocessors are much more expensive, which is alsogenerally undesirable.

One might look to a solution to the computer speed barrier reached inconnection with mainframe computers that, at first glance, mightsuperficially appear to offer solution to the processor speed limithere. A theory of distributed processing allowed division ofcalculations amongst a multiplicity of slower computers and the resultsof the separate computations are combined into one, thereby achievingthe result in the same time as the faster computer, but with slowerspeed lower cost processors than a more expensive mainframe. Theapparent programming complexities in such an alternative appear as anobstacle to implementation. Even so, such theory does not offer any cureto the EMI problem endemic in the present power controller design.

Accordingly an object of the present invention is to reduceelectromagnetic interference within a ELMC.

Another object of the present invention is to minimize the number ofparallel electrical leads required on the interconnecting backplanemember of a modular power controller system.

A further object of the invention is to eliminate the necessity for adata multiplexing card in an ELMC.

A still additional object of the invention is to provide an all solidstate ELMC.

The accomplishment of the foregoing objects provides a novel ELMC thatis of lower cost, smaller size, and lesser weight and greaterreliability than prior ELMC's, which, accordingly, is an ancillaryobject of the invention.

SUMMARY OF THE INVENTION

The novel system architecture identified with the present invention isthat of a serial digital bus directly interconnecting the microcomputeron the controller card with a distributed microprocessor on each of theindividual satellite cards containing the power control devices. Thenovel architecture allows the elimination of data multiplexing cards andminimizing the presence of signals on the electrical interconnectionbackplane card.

In accordance with the foregoing objects, the improved power controllerincludes lower cost low speed satellite or slave microcomputers embeddedwithin the satellite load cards to control a number of semiconductorpower switches that are associated with corresponding individualelectrical loads. The principal or master controller microcomputer onthe controller card communicates bilaterally with each of such slavemicrocomputers via a serial data path that extends along the backplanecard and interconnects the former computer with each of the satelliteload cards, issuing commands in digital serial form. Those commands arereceived by the addressed slave microprocessor, and is interpreted andacted upon by controlling the semiconductor power switches associatedwith the respective slave card.

In accordance with the foregoing objects, the improved ELMC includes lowcost, lower speed microcontrollers used in a distributed command andcontrol architecture that works in concert with the primarymicrocomputer, earlier described. For purposes of description, suchdistributed microcontrollers are sometimes herein referred to as"satellite or slave" microcontrollers.

The slave microcontrollers are typically single chip microprocessorswith integrated analog and digital interfaces. In one practicalembodiment, as example, such slave microcontroller comprises a 16 bit,12 Mhz, computer with Random Access Memory (RAM), Read Only Memory(ROM), analog to digital converter (A/D), eight channels of analogmultiplexing and multiple digital discrete inputs and outputs alllocated upon a single chip, which is in contrast with a typicalmicroprocessor, which only contains the computer, memory and paralleldigital bus interface located on a single chip. Each such slavemicrocontroller is placed on a respective card, referred to as a loadcontrol card, together with several power control devices or SSPCs.

Each such slave microcontroller and its associated interface circuitryis responsible for closed loop data acquisition, data processing, andcontrol functions associated with the few power control devices locatedon the same load control card. The distributed slave microcontrollersare in periodic communication with the higher level microcomputer withinthe ELMC. The foregoing contrasts with the prior ELMC's, wherein all ofthe power control devices were ultimately directly controlled by asingle microprocessor in a centralized architecture.

The ELMC's principal or master microcomputer is mounted on a card,referred to as the "controller card", together with the internal andexternal communications hardware. The master microcomputer communicatesbilaterally with each of the slave microcontrollers via a serial digitaldata path that extends along the interconnection card, referred to asthe "backplane", that interconnects the principal microcomputer with theslave or satellite microcontrollers distributed amongst the load controlcards, issuing commands and data in serial digital form. Thatinformation is received by the addressed slave microcontroller, isinterpreted and acted upon thereby to control the SSPCs on therespective load control cards. The slave microcontrollers acquires andprovides status and diagnostic information in serial form to the mastercontroller along the same serial bus.

It is appreciated that the invention utilizes an all solid statearchitecture. However, when replacing magnetic, latchingelectromechanical relays with solid state counterparts, SSPCs, one mustanticipate and compensate for the potential failure mode of all SSPCs.As those skilled in the art appreciate, when electronic control circuitbias power is lost, the solid state power electronics that is conductingcurrent to the load at that time, loses supply voltage and inadvertentlyshutdowns, interrupting load current. Such a scenario is recognized asdangerous in many vehicle implementations. Further, modern SSPC devicesinclude the ability to change or program the operationalcharacteristics, such as overcurrent trip characteristics. Theoperational performance configuration data that is programmed into theSSPC device is also susceptible in many cases to loss of supply voltage.

In accordance with an additional aspect to the invention, novel circuitmeans are included to ensure that the semiconductor power switches holdtheir last set state in the event of a primary system power supplyfailure, whereby those semiconductor switches emulate the familiarelectro-mechanical mag-latch switch.

In the preferred form, the invention includes a default command channelvia a hard-wired data path that is daisy chained between the mastercontroller and each of the satellite load cards, ensuring operatoravailability of a fixed default command for the separate load cards thatoverrides any configuration commands from the slave microcontroller. Inthis an initial default operating configuration for the load powerswitches, maintained in the master controller, is sent via anotherserial data bus, separate from the serial data bus, to each of thesatellite cards, where that default configuration information ismaintained available. In a practical embodiment the foregoing isaccomplished by digital feed-in, feed-out devices, such as a serial toparallel shift register on each satellite card, with the shift registersformed in a daisy chain arrangement. By supplying a hard-wired overridesignal, the load power switches are configured to such stored defaultconfiguration.

For additional reliability a shadow master controller is included. Theprincipal microcomputer will be redundant to provide a fail safecapability. That is, a spare or back up microcomputer is included on thecontroller card that may be switched into the circuit to substitute forthe primary microcomputer in the event the latter fails.

The foregoing and additional objects and advantages of the inventiontogether with the structure characteristic thereof, which was onlybriefly summarized in the foregoing passages, becomes more apparent tothose skilled in the art upon reading the detailed description of apreferred embodiment, which follows in this specification, takentogether with the illustrations thereof presented in the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the Drawings:

FIG. 1 is a functional block diagram of the improved modular solid statepower controller;

FIG. 2 is a partial pictorial view of the physical arrangement ofcircuit boards within an improved modular solid state power controller,illustrating the orientation of the cards, including the backplane;

FIG. 3 is a block diagram of another embodiment of the invention thatshows in greater detail the relationship of the invention to externalapparatus and reliability enhancing features;

FIG. 4 is a schematic block diagram of an embodiment of the mastercontroller or microcomputer card used in the embodiment of FIGS. 1 and3;

FIG. 5 is a schematic block diagram of one of the SSPC load cards usedin the embodiment of FIGS. 1 and 3;

FIG. 5a is a schematic block diagram of an alternative embodiment of oneof the SSPC load cards used in the embodiment of FIGS. 1 and 3;

FIG. 5b illustrates a command prioritize circuit used in FIG. 5;

FIG. 6 is a flow chart that aids in the description operation of the"watchdog" protective circuit included within FIG. 5;

FIG. 7 is a flow chart that aids in the description of operation of thedefault command circuit included within FIG. 5;

FIG. 8 is a block diagram of a power failsafe protection circuitincorporated within the power controller of the invention;

FIG. 9 is a partial schematic and block diagram illustrating a novel arcdetection and "snuffing" circuit, incorporated within the powercontroller; and

FIG. 10A and B are schematic block diagrams. Input Output card used withthe described embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1, to which reference is made, presents a functional block diagramof the invention. A master microcomputer or microcontroller 1,illustrated as the processor card, is interconnected via serial datapath bus 3 to each of the solid state power controller ("SSPC") cards,containing the satellite microcomputers, used in the system, four, asexample, 5, 7, 9, and 11; it being understood that fewer or greaternumbers of such SSPC cards may be substituted depending upon therequirements of any specific design. Each of the SSPC cards includes,among other circuits, an embedded microcomputer chip, suitably a lowcost chip, and an electronic power switching device that opens or closesthe a power circuit to an external electric load under control of thatembedded microcomputer chip. Microcontroller 1 and the microcomputerchip are familiar digital computers on a chip, containing memory, aprocessor, and performing functions in accordance with a computerprogram that is installed in the memory. These elements are notillustrated in detail in this figure, but are illustrated in thesubsequent figures and are described later herein at greater length.

Serial bus 3 is bi-lateral. That is, the bus is used by mastercontroller 1 to send digital information in serial form to selectedslave cards, wherein the microprocessor associated with the addressedcard, receives and acts upon the information. Conversely, the bus isalso used by the slave microprocessor to send digital information inserial form to master computer 1, such as information on the status ofthe associated power switch or switches, the detection of an electricalarc and/or any other diagnostic information the slave computer isdesigned to supply.

A power circuit transmission bus 4 is connected to each of the SSPCslave cards. That power bus extends to the load coupling connector 6located in front panel 8, through which the power leads are coupled tothe respective external electrical load circuits controlled thereby. Thepower transmission bus includes a plurality of leads, one for each ofthe individual electrical loads that the power controller is intended tocontrol, by connecting power through to the load or, alternatively,interrupting the power circuit. The bus also includes the inputelectrical power from the external source that serves as the electricalpower to be distributed by the power controller.

Master microcontroller 1 on the controller (processor) card receivessensor data via the management bus 10, which is connected theretothrough coupling 12 at the panel, and receives and sends information tothe external management system via data bus 14 and coupling 16, thelatter typically being a 1553 type coupling. A portion of serial bus 3and power bus 4 are physically located on the backplane circuit board,which is better illustrated, in FIG. 2, to which reference is made.

The partially exploded not-to-scale pictorial perspective view of FIG. 2shows the general mechanical configuration of the components found inFIG. 1. Processor card 1, and SSPC cards 5, 7, 9 and 11 are insertedinto the respective circuit board connectors 17, 19, 21, 23 and 25,where they are held in a parallel position. The circuit board connectorsare affixed electrically and mechanically to an underlying circuit board27 that extends orthogonal to the inserted cards, which is customarilyreferred to as the "backplane". Backplane 27 contains the printedcircuit wiring that defines the communication and power bus which extendin parallel along the length of the backplane. The backplane in turn ismounted within a metal enclosure, represented in dash lines, preferablyone in which the rear end and sides are formed from a single piece ofmetal, such as aluminum, for best heat transfer characteristics andmaximal cooling.

Suitable coupling cables and connectors complete the electrical circuitsfrom the backplane to the panel connectors and the panel is mounted tothe front of the enclosure to allow easy access by the operator. Herethe backplane also contains the printed electric circuitry forconnecting the leads from the cables to the master controller card 1.Where desired, however, connectors may be attached directly to card 1instead, thereby reducing the printed circuitry somewhat on thebackplane, in which case the cables will run directly to the frontpanel. Those skilled in the art appreciate that FIG. 2 omitsillustration of the plated electrical leads found on the backplane andother printed circuit cards and the details of conventional mountinghardware, which are not necessary to an understanding of the invention,and recognize that the mechanical packaging arrangement used for theimproved power control module is entirely conventional in structure andis the same found in the prior power control modules.

It is appreciated that the present power controller of FIGS. 1 and 2 isa sub-system, in which some of the commands that the power controllerfollows is provided by an external operator or automatic system,referred to as a management system, which provides those commands inproper signal form via the communications input 16. Likewise the presentpower controller provides information to that external system, includingprescribed warning signals and the like. The external system is of anypreexisting design, such as is used with the prior power controllerdesigns which the present invention improves upon. Inasmuch as thedetailed design of such management systems are not necessary to anunderstanding of the present invention they need not be furtherdescribed, except in general terms as outlined in the block diagram ofFIG. 3, next considered.

For convenience elements identified by number in the preceding figureswhere they appear in FIG. 3 are identified by the same number. Thusthere is shown the microcontroller card 1, serial bus 3, satellite SSPCcards 5, 7, and 11, power bus 4, which underlies the dash line in thefigure. Signal and control communication with an external command anddata management system, represented as block 18, illustrated to theupper left, is accomplished via couplings 12 and 16 and the associatedtransmission lines represented in dash lines.

Each embedded microprocessor on the SSPC card controls a plurality ofindividual electrical load circuits, four in the example given. Thuseach satellite card contains four power semiconductor switching devices,suitably MOSFET power transistors, not illustrated in the figure, andthe microcontroller has sufficient outputs to individually control atleast that number. For power on for a particular load, themicrocontroller supplies a bias to the associated semiconductorswitching device and that device is placed in its high conductivitystate, conducting electrical current through the power bus 4. It is seenthat the power bus comprises thus a large number of individual leadsplated on the backplane circuit board that run in parallel along thebackplane in FIG. 2.

FIG. 3 also illustrates additional features incorporated within thepreferred embodiment of the invention. A default command circuit isprovided that provides a default command to the satellite load controlunit. This is a hard wired circuit. As later herein discussed, thedefault command, though present at each of the SSPC load control cards,is activated only at the command of the operator, who operates anactivation switch, and thereby overrides any commands issued to the SSPCcard via serial bus 3. A second serial output from master controllercard 1 is wired, via the backplane, to an input of a first slave card inthe series, here card 11. In turn the satellite card contains an outputthat is hard wired, also via the backplane, to an input on the nextsucceeding satellite card in the series. In turn the next card containsan output, hard wired to an input on the next card. Such wiring isaccomplished for each of the satellite SSPC cards 5, 7, 9 and 11, or inmore general terms, where the number of cards is N, for N-1 cards. Thiswiring of the satellite card is referred to as a "cascade" or "daisychain" wiring.

In operation master controller 1 issues the address and command via theserial data bus 3. The master controller also clocks out a set ofdefault commands via output 43 as a serial bit stream, containingdefault commands for each of the load SSPC load control units in thesystem. That bit stream is clocked into the first SSPC card in the daisychain. With additional clock pulses, that data is clocked out of thefirst SSPC card in the series to the next, and so on to the next SSPCcard in the series. Suitably that form of serial input and output isaccomplished in the SSPC cards with a conventional serial to parallelshift register, as discussed in greater detail in connection with FIG.5, that receives information in serial form and as the capacity of theregister is exceeded outputs those same data bits on a first-in,first-out basis, while also providing a parallel output equal to thenumber of bits in the shift register between successive clock pulses.The master microcontroller assembles the default command for each SSPCcard in the chain in reverse order into the serial bit stream. Whenclocking is completed, the default command intended for the Nth SSPCcard, which is clocked out first in the bit stream, is resident in theNth SSPC card's shift register.

The foregoing places the default command data at the respective remoteSSPC card, awaiting possible use. Should the vehicle operator find needfor any reason to override the commands issued by microcontroller 1 viathe serial bus, the operator activates a switch, the panic button so tospeak, which allows the known default commands to take priority. Aconventional prioritizing logic circuit resident in each card insuresthat commands otherwise received at the SSPC unit is overridden.

Other checks may also be included in the system, such as a "watchdog"circuit, that may additionally included as a second priority to thedefault in the case the slave microcomputer fails. The latter isincorporated in a preferred embodiment of the invention later describedin this specification.

For additional reliability another controller is provided to shadow theprincipal master controller as indicated at 1' in FIG. 3, wired onto thesame circuit board, referred to as the shadow microcontroller, and aback up power source, not illustrated, is also preferably included.Should one of the principal units fail, the shadow or back up unit isswitched into place to perform the functions of the failed principalcomponent.

The power supply controller is also easily reconfigured to allow thecontroller to interface with additional external equipment requiringdiscrete command and data signals, such as those designated AUXEQUIPMENT in FIG. 3. The former provide signals in analog form and thosesignals need be "conditioned" and transformed to digital form. This isaccomplished by including an appropriate Input Output card 45 within theELMC. That reconfiguration is easily accomplished by adding a suitableelectrical connector to the backplane, in FIG. 2 allowing the I/O cardto be contained within the package and communicate with the serial bus3. An example of the circuit of a suitable I/O card is illustratedschematically in FIG. 10, described later herein. Electrical connections48, 49 and 50 are accomplished by additional cabling.

Reference is made to the schematic block diagram of FIG. 4, illustratingthe master microcontroller card 1. Microcontroller la is the principalcomponent of microcontroller card 1. It receives the input information,processes that information, issues commands to the slave microcomputersin the satellite cards in serial form, receives digital information fromthose satellite computers, and receives and sends digital information tothe external management system. To the right of controller la are shownthe components for communicating with the external management system,including translation semiconductor chip 22, transceiver 24, isolationtransformer 26, parallel to serial converter circuit 28, serial toparallel converter circuit 30 and flash ram 32.

Thus data transmitted from the external management circuitry to thispower converter is, in this example, transmitted in serial form, arrivesvia coupler 16, is coupled through isolation transformer 26 and input totranslator chip circuitry 22, where it is decoded/encoded and input tocircuitry 30 where the command is converted from serial form to parallelform, the form required by the particular microcontroller, and isapplied to an input to the controller. In the event the rate of receiveddata is too great for microcontroller la to handle, the data is enteredinto temporary storage in a flash ram chip 30, which thereby serves as abuffer, and is read out from the flash card under control of themicrocontroller.

When controller la sends data to the external management system, theinformation is output in parallel form to converter 28, which outputsserial form information that is applied to translator 22, which encodesa serial digital format and to transceiver 24 wherein it is converted tothe specified electrical characteristics for serial transmission andfrom which it is output through transformer 26.

A signal indication that an incoming word has been received is providedon the lead labeled VALID WORD. A signal indication on the lead labeledENCODE ENABLE initiates transmission of a word. Oscillator 31 is thesystem clock which provides periodic clocking signals to the controllerla and translator 22.

Controller 1a contains an asynchronous serial port (UART) 33 forcommunications to the serial bus 3, earlier described. In normaloperation switch contact 35a is normally closed to complete theelectrical circuit from port 33 to the serial bus, allowing themicrocontroller to send commands along the data bus.

Leads 36, 40 and 41 to the microcontroller and mag-latch switch 35 andassociated capacitors Cl and C2 are provided for control of the shadowcontroller, the redundant controller provided as a backup earlierbriefly discussed. The shadow microcontroller, not illustrated in FIG.4, and microcontroller 1a periodically send one another check bits. Areceived check bit is interpreted by the receiving controller as meaningthe sending controller is operating satisfactorily. Assume for example,that microcontroller la becomes disabled and is no longer able to sendcheck bits. The shadow controller interprets the absence of such checkbits as microcontroller 1a has failed and that the shadow controllermust perform the functions instead. In accordance with its program theshadow controller sends a pulse of current over lead 41, which iscapacitively coupled through capacitance C1 and energizes the OFF coilof mag-latch switch 35. The mag-latch switch is a conventional bi-stableelectromechanical switch containing two electromagnet coils. Whenenergized briefly, one coil will latch the switch in one state; when theother coil is so energized subsequently, the switch latches in the otherstate. Upon receiving the current impulse, the mag-latch switch switchesinto its other bi-stable state and opens contact 35a, which preventscontroller 1a from further outputting commands to the serial bus 3, andthe latch switch remains in the off-state.

When the power controller is first turned on and initialized,microcontroller 1a sends an impulse of current through capacitor c2,which energizes the ON coil, ensuring that mag-latch switch 35 is in itson state closing contact 35a. Microcontroller 1a also sends asimultaneous pulse over lead 40 to the corresponding mag-latch in theshadow microcontroller to ensure that such mag-latch switch is in itsOFF state with the electrical contact, corresponding to contact 35a inFIG. 3, is open, thereby preventing the shadow controller from issuingcommands to serial bus 3.

Leads 38 and 39 are provided for the operation of the hardwired verifycircuit, earlier herein discussed in connection with the block diagramof FIG. 3. Lead 37 to the IO card couples "handshake" signals to the I/Ocard for synchronizing data exchange between the I/O card and the mastercontroller 1a. Lead 38, labeled hardwired serial data is the lead overwhich the output bit pattern is provided to the verification circuit onthe slave load control cards, elsewhere herein described in FIGS. 3 and5; and lead 39 provides the clock signals for that verification circuit.

Reference is next made to FIG. 5, which presents a schematic blockdiagram of a first embodiment of the satellite SSPC cards, used in theembodiment of FIGS. 1 and 3, such as SSPC card 11. It may be noted thatan alternative embodiment for a satellite SSPC card is illustrated inFIG. 5a, which is described later herein. The embodiment of FIG. 5,includes microcontroller 11a, a programmed microcomputer containing aprogram in memory, which in a specific example may comprise the 87C196KCcontroller chip manufactured by the Intel company of Santa Clara,Calif.; an associated clock oscillator 11b a serial interface circuit51, control status bus 53 and the four load switching circuits SSPC-1,68, SSPC-2, 69, SSPC-3, 70, and SSPC-4, 71. The power bus Pb1, coupledto the slave load control card via the backplane, delivers the DCcurrent from the external power supply, which is distributed by the SSPCunits to the various electrical loads, through the respective SSPC loadoutputs, designated as leads 4a, 4b, 4c and 4d, respectively.

For convenience the power supply connections to the various circuitelements, including that applied at Vref of slave microcontroller 11a,not necessary to an understanding of the invention, are not illustrated.However, as discussed later herein in connection with a specific featureillustrated in FIG. 8, two independent regulated DC power supplies areincluded in the preferred system.

It is noted that some aspects of a practical embodiment of an inventionare illustrated in greater detail than may be necessary for anunderstanding of the invention, such as in connection with the number ofdigital bits from a port and the like. In accordance with drawingconvention, the number of digital bits output in parallel from a port isrepresented by a number; the number of leads in a line is sometimesrepresented by a slash across the line and accompanying number.

Slave microcontroller 11a receives and processes the command informationaddressed to it appearing on serial bus 3, which is supplied in a highlevel language. The microcontroller translates that command and outputsa lower level code to which the selected one of the SSPC MOSFET powerswitching devices ultimately responds as later herein described ingreater detail, by completing or alternatively interrupting theassociated electrical load circuit 4a-4d. Microcontroller 11a outputs acommand from ports 1 and 2 along bus 53 as a sixteen bit code.

In this embodiment, the particular microcontroller chip selected forreasons of practicality is limited to thirty two input output ports,while the circuit has forty I/O's. To account for 40 locations thus, thecircuit includes address decoder logic 59, latch 60, ram 62 andprogrammable peripheral interface chip 61. Thus information from ports 3and 4 of microcontroller chip 11a are multiplexed from chip 61 as acommand and status's from the SSPC's. It is appreciated that a suitablemicrocontroller may be constructed on a custom basis that would becapable of handling the number of addresses required for the practicalembodiment. To do so, however, would greatly increase the cost of thechip, which is not desirable.

The hard wired daisy chain default command circuit was earlier describedin connection with FIG. 3. The daisy chain circuit for extending thedefault command data from the master microcontroller and between thesatellite SSPC cards enters the circuit at 43 and exits via lead 43. Aclock signal that is supplied by master controller 1a in FIG. 4 alsoextends along the backplane between the master controller and each ofthe satellite boards which is also shown to the left in the figure as"CLK IN". The clock, data in and data out leads are coupled to thecorresponding inputs and outputs of serial to parallel shift register58.

In operation, assuming the shift register circuit has been initialized,as subsequently described, data bits are serially applied on lead 43 bythe principal microcontroller 1a and are clocked into shift register 58.As that operation progresses, when the number of digital bits receivedexceeds the capacity of the shift register, an overflow condition isreached in which, as is known, the shift register empties the old dataon a first in first out basis with each additional clock pulse received.The excess bits are clocked out from this shift register into the nextshift register in the next load control card via Data Out lead 43n,while the present shift register receives additional bits; and so on,from that shift register to the next, continuing until microcontroller1a has sent a sufficient parade of bits to fill all of the shiftregisters.

The foregoing creates a particular pattern of bits in each of the shiftregisters, including shift register 58 in this figure, that appear as aneight bit parallel output obtained from the shift register. Thesatellite's shift registers are daisy chained together and the paradepropagates through, bit pattern propagates through from the master tothe respective satellites. By design, each "bit pattern" is applicableto only one of the many satellite load cards. As an example in theembodiment illustrated this overall parade of bits required to fill allof the shift registers in a four load card system is thirty two bits inlength. However, the parallel output of the shift register is inhibitedunless a signal is applied at "MSCOMP WOW safe recovery" and to achievethat signal the operator must turn on an external "DEFAULTS" switch, notillustrated. Effectively, thus the output of the shift registerindicates a command to be implemented or a do not care and that commandis registered and stored at the load control card awaiting possibleimplementation.

Returning to FIG. 5, the embodiment includes command prioritize circuits54, 55, 56, and 57. The highest level priority is at the left input inthe figure, the second level priority is the middle input and the thirdlevel priority is at the right of the priority circuit block. Theprioritize circuits are conventional logic circuits formed ofcombinations of gate circuits and/or resistor diode combinations, whichassign a priority to multiple input signals, permitting only the highestlevel priority through. The prioritize circuit outputs a two bit digitalcode to the control and enable inputs of the associated SSPC.

Returning to FIG. 5, two bits of the parallel output from shift register58 are assigned to a first level priority input of each of the commandprioritize circuits 54, 55, 56 and 57. This gives the default command,the highest priority, but only in the event the operator operates theDEFAULTS switch or a comparable hard wired default signal is appliedautomatically by external equipment.

Microcontroller 11a supplies the discrete load command informationdecoded from serial bus 3 as a discrete digital signal, the number ofbits in the signal, being a design choice for the SSPC design. Assumingthat neither the default command or the watchdog circuit 63 provides anoutput, the command prioritize circuits 54-57 passes the load controlcommand to the input of the respective SSPC power transistor circuits68, 69, 70 and 71.

Following receipt of first transmitted data, the master microcontrollerreinitializes the shift registers. Master microcontroller 1a in FIG. 4produces additional clock pulses to shift the data out of all of theshift registers. The data is shifted out serially, under control of theclock pulses, through the data output 43n and is input to the data inputof the next satellite card and ultimately is sent back to mastercontroller 1a on the controller card. According to its program, themaster controller recognizes the returned bit pattern as the same asthat sent, and deduces that the shift registers in the daisy chain arecleared for the next operation. This is the same process that isaccomplished once the system is first powered up and the system isinitialized, including clearing the shift registers in the daisy chain.

To eliminate the possibility of false SSPC configuration programmingdata or the failure of the slave microcomputer 11a, a unique circuit ispreferably included in the power controller, wherein the powercontroller is said to be fault tolerant. This is called the watchdogcircuit.

Returning to FIG. 5, thus, the output from chip 82c55, 61, containingthe command from microcontroller 11a, is input a pulse to "watchdog"circuit 63, shown in block form. The watchdog circuit contains a timerthat resets with each pulse input. The watchdog circuit recognizes thatit is receiving pulses and, therefore, applies a "false" signal outputin parallel to the not input of each of the NOT gates 64, 65, 66 and 67.With the gates thus inhibited, the second input does not pass through.

The second input to gate 64 is the output from block 68 "sspc1flow",which represents the existing or current state of the SSPC from theassociated power switch circuit SSPC1 as output at "sspc1flow"; thesecond input to gate 65 is the output from block 69 sspc2flow; and so onwith the second input of each gate being connected to the "sspcflow"output of an associated one of the SSPC power switches. As long asmicrocomputer 11a functions, thus, those sspcflow signals do not passthrough to the respective prioritize gates 54 through 57.

If, however, the microcomputer fails to write to the watchdog circuit,the watchdog circuit fails to receive a pulse from the slavemicrocontroller within a predetermined period of time, the internaltimer "times out" and the circuits outputs are switched to TRUE, openinggates 64 through 67. The watchdog circuit then gates the outputs ofgates 64 through 67, and the various SSPCFLOW data from the SSPC's68-71, representing the existing or current state, as variously termed,of the SSPC's, either "on" or "off", is thereby applied to the secondlevel priority of the respective command prioritize gates 54-57.

Assuming the DEFAULTS switch has not been operated to give the defaultcommand a higher priority, the outputs of the watchdog circuit overrideany signals applied to the third level priority inputs bymicrocontroller 11a and are applied through the respective commandpriority gates to the control and enable inputs of SSPC 1 through SSPC4. This action effectively latches those SSPC's into their existingstate. No new command information can be entered into the SSPC's. TheSSPC's continue the state, whether conductive or non-conductive, inwhich they were last set.

The steps specified for the watchdog circuit and priority handoff to thenext lower priority check, the hard wired shift register commandverification circuit, is illustrated by the flow chart of FIG. 6. Themicrocontroller initializes the shift register pattern. Themicrocontroller then removes the wow=0 and, in the next step, sends theaddress and command data to each of the load control cards, such as thatillustrated in FIG. 5, via the serial data bus, to the slavemicrocontroller, such as 11a, which thereby updates the individual SSPCunits on each load control card, such as 68, 69, 70 and 71 in FIG. 5, inthe manner earlier described and writes the proper code to the watchdogcircuit 63. The watchdog circuit contains an internal timer that resetseach time a pulse is received from the slave microcontroller. If timeout=1 is negative, a portion of the cycle is repeated causingmicrocontroller 11a to again update. If that timeout is positive,meaning a failure of the slave microcontroller or its software, then theSSPC units are maintained in the last state. If a safe recovery is lateractivated, then the shift register verification procedure is allowed totake over and, as the next highest priority, ensure a correctverification.

It is noted that each SSPC 68-70 includes voltage and current sensingoutputs, represented at the encircled letter A, a that provides ananalog signal of the voltage and current at the load circuit. Thoseoutputs are connected to the input of slave microcontroller 11a, alsolabeled encircled letter A, and the microcomputer's internal analog todigital converters, not separately illustrated, converts thatinformation to digital form for processing by the microcomputer inaccordance with the microcomputer's diagnostic routines.

Reference is now made to the alternate embodiment of FIG. 5a in whichcorresponding elements to those in FIG. 5 are identified by likenumbers. The command prioritize circuit and the watchdog circuit of FIG.5 is unnecessary and is not present in this embodiment. In thisembodiment, software cross checking and verification is accomplished bypermitting the master microcontroller to verify that the correct commandis about to be sent to the SSPC, while maintaining the command in abuffer of sorts, prior to finally sending the command.

The appropriate DC voltage is applied at Vref and the slavemicrocontroller has the associated clock oscillator 116'. The voltagesense and current sense monitoring inputs of the microcontroller, whichmonitor the respective voltage and current of each load circuitassociated with an SSPC, such as illustrated at SSPC's 68-71 in FIG. 5,correspond to the encircled A locations in FIG. 5, are shown. Thoseinputs include suitable input electronic limit and protection circuits,as at 131 and 132 connected to PO.1 and PO.7, the intermediate onesPO.2-PO.6, not being illustrated. The slave also includes a write outputat WR and a read output at RD.

The pair of shift registers 58'a and 58'b are placed in series with theserial output of 58'a feeding into the serial input of register 58'b.Those two shift registers are formed into the daisy chain, as in theprior embodiment, with the corresponding pairs of shift registers on theother load control cards. Here the output of the last shift register inthe formed daisy chain is returned to the hardware serial data pin 39 inFIG. 4 of the master microcontroller 1, not illustrated. Unlike theprior embodiment of FIG. 5 in which that last serial output of the lastshift register in the chain is not utilized. The hardware clock outputof the master microcontroller indicated at Master Clk1 in this figure isconnected, via the backplane card, to corresponding inputs of both shiftregisters illustrated and in multiple to the like inputs of all othershift registers having the same function on each of the load controlcards.

In this embodiment the master microcontroller 1 (FIG. 4) is programmedto use pin 39 as a serial data input, whereas in the prior embodimentthe master controller was programmed to use that pin as a serial dataoutput. As becomes apparent, since a greater quantity of commandinformation is provided in this embodiment because of the current tripadjustment of the SSPC's, the embodiment includes more than twice thenumber of shift registers as before.

In the embodiment of FIG. 5a, all command and configuration data fromthe master microcomputer 1 (in FIG. 4) is downloaded as serial digitaldata to the slave microcontroller 11a via internal serial bus 3. Havingreceived that data, slave microcontroller 11a then issues thecorresponding decoded command and configuration information via outputsP3 and P4 to the first stage of latches, 120 and 121, and is writteninto those latches by issuing a write command at WR. A copy of thatlatched information is applied to a parallel input of the shiftregisters 58'a and 58'b, but that data is not inputted until the mastermicrocontroller issues a load strobe pulse at Master LD/Shft1. Themaster controller next verifies that the proper command data is residentin each of the load control cards.

Assuming all shift registers are initialized, the master controller thensupplies a load pulse via Master LD/shft 1 input and the shift registersload the data present at D8-D15 and D0-D7 buses from latches 120 and121, respectively, in parallel into the respective shift registers. Nextthe master microcontroller supplies clock pulses via MASTER CLK1 to theshift registers 58'a and 58'b and thereby shifts that data seriallyalong the chain of shift registers in all the other load control cards,returning that data in a serial data stream back to the mastercontroller, via pin 39. This leaves a copy of the configuration commandinformation in the set of latches 120 and 121, which essentially servesas a buffer.

The master controller receives that serial data stream from the shiftregisters and compares the command data for each load control card withthe corresponding data in memory, a basic comparison operation, therebyverifying that the individual on-off and configuration informationappearing in that data stream for each SSPC, is correct. That is, thereturned information matches the corresponding information that themaster controller retained in memory and had earlier sent into theregisters.

Once the master microcontroller inspects the returned command data andverifies that the command data is correct, the master microcontrolleroutputs a digital pulse or strobe MASTER1 STRB, as variously termed,through OR gate 131 to the second stage of latches 122 and 123. Inresponse, the second stage of latches, 122 and 123, outputs the data onthe output data bus, which is an eight bit parallel bus as shown, toassociated SSPC units 68', 69', 70' and 71', not illustrated in thisfigure, via respective opto-isolator units, such as 127, and CTL leads,such as 130, illustrated in connection with the first SSPC 68'.

The foregoing steps and the action of microcontroller 1a is illustratedby flow chart of FIGS. 7. As specified by the steps in the flow chart ofFIG. 7, the master microcontroller 1a of FIG. 4 issues a command to theSSPC via the serial data bus 3 as earlier described; it then producesthe load shift output and clock pulses to the shift registers on theload control cards via a hard wired circuit to shift the parade of bitsback to the master controller where the bit pattern is checked to verifythat the shift registers contain the proper commands for each of therespective SSPC power switches on the load cards. If the verification ismade, the master controller issues the strobe command STRB1 to activatethe load commands at the SSPC load control cards, which is accomplishedin the manner earlier described. If the master microcontroller cannotdetermine whether the command was shifted, it requests the back upmaster microcontroller to check it out. If positive confirmation is madeby the back up master microcontroller, the procedure continues toactivation as before; if not the procedure grinds to a halt and stops.

The embodiment of FIG. 5a does not require either a watchdog circuit ora command prioritize circuit as did the embodiment of FIG. 5, earlierdescribed, since the command signal to the SSPC is verified to becorrect prior to actually outputting the command to the individualSSPC's.

While the daisy chained serial to parallel shift registers in theembodiment of FIG. 5 was used to receive and hold the defaultconfiguration command's sent by the master microcontroller for theindividual power control cards, in the embodiment of FIG. 5a the reverseis found. That is, the daisy chained shift registers are operated in aparallel to serial mode and are used to return a copy of the commandreceived from the slave microcontroller to the master controller,allowing the master controller to inspect the returned copy and verifythe accuracy of the command data retained in the latches on the loadcontrol card, prior to implementing the command.

A second copy of the shift registers 58'a and 58'b is provided byserially connected shift registers 58'a' and 58'b', illustrated on theupper right of FIG. 5a. The connections Master Clk2, Master LD/shft2,D8-D15 and D0-D7 and Shift In2, correspond to those earlier describedfor the principal master microcontroller. Inputs D8-D15 and D0-D7 areconnected to the output of latches 120 and 121 by appropriate leads, notillustrated. These redundant latches allow the shadow master controller,earlier described in connection with FIG. 3, to have the same level ofverification as the master microcontroller in the event of a failover.

An additional pair of latches 128 and 129 are shown in the bottom middleof FIG. 5a. The inputs of those latches are connected via the respectivebuses 128b and 129b to the outputs of latches 122 and 123. This places acopy of the load configuration information at the respective latchinputs. The outputs of latches 128 and 129 are connected, respectivelyto the P4 and P3 locations, earlier referred to as outputs. Locations P3and P4 are under control of the slave microcomputer and are programmablein accordance with the microcomputers program. Thus those locations maybe either used as outputs, as earlier described, and at other occasionsduring the course of the computer program, those locations may serve asinputs and be read. Should the microcomputer issue a read command at RDduring the run of its program, the latches 128 and 129 output theearlier received data at P4 and P3, respectively, the microcomputerreads that information and may thus check the load configurationlocally.

In the embodiment of FIG. 5a, each SSPC may be configured to operate inone of two modes, the circuit breaker mode and the power controller modeand, further, in the power controller mode, the SSPC may be furtherconfigured to different trip current levels, as example, five amps, tenamps and so on.

When configured in the circuit breaker mode, the SSPC is normally "on"and continuously conducts current, opening only when the current sensedbecomes excessive, such as occurs if the electrical load, such as airconditioner develops a short circuit. Since the SSPC is a powertransistor, a device that does not normally conduct current unless abias control voltage is present, when power is first applied to power upthe system, if the circuit breaker mode is implemented the load commandinformation provides the bias to set the power transistor to "on".

When configured in the power controller mode, wherein the power is to beintermittently applied, such as turned on every now and then, totemporarily supply power to some equipment, such as a fan or pump, asexample, the SSPC is normally "off", that is, is in a electricallynon-conducting state. It is turned "on" only when needed by themicrocontroller and then only for the period that the microcomputerallows. To switch the SSPC to its "on" state, the microcontrollersupplies a signal voltage that biases the switching transistor to itsconductive state. That signal is applied to the CNL and ENBL inputs,shown also in FIG. 5, of the SSPC.

Moreover, the SSPC power transistor load control circuits in FIG. 5a,corresponding to 68, 69, 70 and 71 in the prior embodiment of FIG. 5,include a feature that allows the SSPC, when in the power control mode,to have its current trip level set to a selected level, amongst one ormore current trip levels. This is accomplished by providing amulti-level output at latch 122. That output is converted by converter127, shown to the right in the figure. Converter 127 is a conventionalopto-electric device containing a light emitting diode and a coupledphototransistor in which the transistor's output is a function of thelight produced by the light emitting diode. By conventional detectioncircuitry in the SSPC, such as 68, the trip current level is determinedby the current level produced by the phototransistor in converter 127.

Each SSPC also provides information on its status, such as whether thecurrent level has tripped an interrupt, as example, which information ispresented in and outputted as two data bits. One of those outputs isrepresented at 133. With four such SSPC's on the card a total of eightbits is inputted to the P1 input of slave microcontroller 11a in FIG.5a. The local power control card thus includes self diagnostic abilityand information resources. It may also send that information to themaster digital controller.

The circuits of FIG. 5 and 5a, earlier discussed, also includes a novelcircuit that allows a MOSFET transistor to emulate the bi-stableperformance of the electromagnetic mag-latch switch. The characteristicsof that electromechanical switch were earlier described in connectionwith FIG. 4. The mag-latch switch contains two electromagnetic coils,which are separately energized. The switch latches into the stateassociated with the last coil to be energized. Subsequent currentfluctuations in that coil cannot change the switch's state.

In contrast power electronic switching devices, such as mosfettransistors, require a bias voltage in order to remain in a currentconducting state. Should the bias voltage be withdrawn, such as by afailure in the power supply, however temporary, the power switchingdevice will switch to its non-current conducting state. This is notdesirable. As example, should the power controller be employed as partof an aircraft's electrical system, one of the controlled loads may bean electric fuel pump. One obviously would not wish the fuel pump todiscontinue on aircraft take off, in the event of a temporary loss ofpower or malfunction in the power controllers power supply. The fuelpump should remain operative.

The bistable characteristic as allows mag-latch emulation is obtained bya redundant, backup, power supply arrangement. First, there are twoisolated bias voltage supplies to all circuitry in the ELMC. Second,these supplies are regulated and diode isolated on each card. Third, apower supply is incorporated into the SSPC electronics to provide biasfor maintenance of the last command state, even in the event of the lossof the first two power supplies.

That protection circuit is illustrated in greater detail in FIG. 8 inblock diagram form, to which reference is made. As illustrated, thispreferred form of the invention includes a second power bus Pb2extending along the backplane card to the load control card. That secondpower bus is in addition to the power bus Pb1, earlier described inconnection with the prior figures, such as FIG. 5, but which was notearlier illustrated. Power bus PB2 is coupled to a conventional DC to DCconverter, 103, which down converts the supply voltage, and the voltageis applied to diode 104, located on the load control card, which allowscurrent to flow in only one direction, preventing back flow. From there,the dc supply current is fed through a conventional regulator 102 to thepositive supply input of the SSPC 68. Likewise the other power bus Pb1is connected through DC to DC converter 101 to protective diode 106 andthat diode is also connected to regulator 102, where it propagates tothe same positive supply input to the SSPC. From the SSPC positivesupply input, the DC current is applied through another protective diode100, located within the SSPC and from there to the internal power bus110, which in turn is connected internally to the supply inputs of thesemiconductors, not illustrated, within the SSPC.

The two power supply circuits are thereby placed in parallel circuit.Should either one fail, the current will be supplied to the SSPC by theother, while the diode in the other circuit prevents current fromflowing from the other power supply to the supply that failed.

The foregoing connection from the output of the DC to DC converters isalso made to corresponding pairs of regulator and diode arrangement,also located on the load control card, associated with each of the otherSSPC's located on that card, such as SSPC's 69, 70 and 71, illustratedin FIG. 5 and those used in connection with FIG. 5a. Such additionalcircuits and components, however are not necessary to an understandingof the invention and are therefor not illustrated.

The principal power bus Pb1 is also connected by lead 4 to the loadinput of the respective SSPC. As earlier described At the output of SSPC68, power bus Pb1 is connected to the electrical load circuit controlledby the SSPC, when the transistor switch located in the SSPC, heresymbolically illustrated by the open switch 107, is placed in itselectrically conductive state, effectively closing the switch.

Another DC to DC converter 108 is located within the SSPC. Converter 108has its input tapped to the incoming power line Pb1 and, like the otherconverters, down converts the voltage to that suitable for operation ofthe semiconductors, not illustrated, located within the SSPC. The outputof that internal converter 108 is in turn connected through anotherprotective diode 109, which allows only unidirectional current flow, andfrom there the current is supplied to the internal power bus 110.Effectively thus, this forms a third power supply for internallypowering the SSPC's semiconductors. Assuming thus logic the Vcc powerbus for the logic circuitry fails, and electrical current is no longersupplied to the positive supply input of SSPC 68 via regulators 102and/or 104, supply current remains available to the SSPC's internalcircuits through converter 108 and diode 109. Thus, assuming the powertransistor is in its electrically conducive state, ie. switch 107 isclosed, at the time of such Vcc power bus failure, which would normallyremove the bias voltages from the power transistor, switching thetransistor off, the transistor, nonetheless, remains in thatelectrically conductive state because the bias voltages to thesemiconductors are now supplied through converter 108 and diode 109.

The slave monitors power output voltage and current analog's via ananalog port associated with the microcontroller to detect voltage when aSSPC has "tripped". If this occurs, a clamping control signal should beapplied. The SSPC clamps for any trip or off command. Arc detection isaccomplished by the same circuit.

The preferred form of the invention incorporates a novel arc detectionand "snuffing" circuit, advantageously formed in conjunction with theslave microcontroller, illustrated in FIG. 9 in partial schematic andblock diagram form. In the load control card, the power line extendsfrom the power bus, Pb, through to the load via lead 4, earlierdescribed. That current path is completed by a solid state MOSFET switch93, which is gated to the "on" condition by an associated controlcircuit earlier described, represented in the figure by block 97. Thatswitch forms part of the SSPC power control circuit earlier discussed. Acurrent sensor 95 is included in that load current path. A transistorswitch 91 has its output connected between the power lead 4, where thelatter lead exits the load control card and extends to the backplanecard for distribution to the associated electrical load, and ground, inshunt of the load. Transistor switch 91 is normally off, that iselectrically non-conducting. With proper output from control circuit 98providing an "on" bias to the transistor, the transistor switch switchesinto the conductive state, providing a low resistance current path toground, shunting the electric load.

The output of the current sensor 95 is coupled via lead 94 to one of theanalog to digital inputs of the slave microcontroller 5' situated on theload control card, whereby the information of current level is availableto the slave microcontroller, and to the control circuit 97 forsemiconductor switch 93. Another lead 92 connects line 4 to anotheranalog to digital converter in the microcontroller, and makes availableto the microcontroller the level of line voltage.

In operation should the current sensor indicate an overcurrent conditionor "overload", control circuit 97 supplies the proper bias to switch 93to off, interrupting current to the load. A simple subroutine in themicrocontroller's program causes the microcontroller to check thevoltage and current inputs provided at leads 92 and 94, to make thedetermination of the existence of an arc condition and to initiate theappropriate control outputs.

Returning to FIG. 9, when the microcontroller senses the appropriatelevel of line voltage and current that is recognized as a signature ofan electrical arc condition, the controller 5' also issues a command tocontrol circuit 98. In turn that control circuit supplies an input tothe control of transistor 91. The transistor then switches "on" andconducts current between the line 4 and ground potential, effectivelyextinguishing any electrical arc.

The foregoing overload and arc snuffing circuit is illustrated for onesuch SSPC circuit. That circuit is reproduced in each of the other SSPCcircuits on the load control card; and each such circuit is connected tothe single slave microcontroller on the load control card throughseparate analog to digital converter inputs. Where as here the foregoingchecks are made with a single microcontroller, the checks of each SSPCis made in a sequential order during the run of the arc check subroutineto the computer program.

It is known that a particular current and voltage signaturecharacterizes an electrical arcing condition in a power distributionfeeder. When one electric wire, maintained at one electrical potentialor voltage, is located in close physical proximity to another object ata different electrical potential, such as a electrically groundedstructure, separated therefrom by a gap, or when a break occurs in thewire, such as is present in contacts within bulkhead connectors, adifference of electrical potential exists across the gap. When thepotential difference across the gap exceeds the insulating voltagebreakdown voltage of air or whatever medium is separating the energizedwire from the other object, an electric arc may form across or "jump"the gap.

When the arc is first formed, a rise in line current is initiallyexperienced, referred to as an overcurrent condition. In prior MCLEsystems, such overcurrent condition typically trips a circuit breaker tointerrupt power to the power line, or in the present invention, thesolid state power control device opens to disconnect the voltage sourcefrom the load.

A problem arises in that the arc condition can be sustained,nonetheless, at least temporarily, even after such disconnection if thearc is "fed" with energy stored in the distribution networks and in theelectric loads, such as by the inherent capacitance therein. Althoughrelatively short in duration, such continued arcing can cause seriousdamage to the power distribution system by degrading wire insulation,creating burnt or broken cabling, or even cause a fire in thesurrounding structure. It is important, therefor, to detect a residual,sustained arcing condition and extinguish that residual arc before anysuch secondary damage occurs. Applicant's recognize that the residualarc in the present system is characterized by low amplitude voltage inthe electrical node supporting the arc, and the power control switch,which opened due to the overcurrent condition at the commencement of thearc condition, has near zero current flow. Therefore, when a tripcondition on the power control device, zero current flow and a residualarc sustaining voltage occur simultaneously in the present system, thecontrol system detects the residual arc condition and extinguishes thatarc.

The residual arc is fully extinguished by shunting the arc sustainingenergy to electrical ground, thereby de-energizing the arc andextinguishing the condition. This is accomplished in the inventiondescribed herein through the use of a shunt transistor switch connectedbetween the distribution line feeder (arc sustaining node) and theground node. While the use of a fast transistor switch to extinguish anarc is believed to be known, in the present system the fast acting solidstate transistor is used in combination with a data acquisition andcontrol technique using the microcomputer, hereafter described ingreater detail, a truly new and unique "fuse" structure is defined.

First, the voltage and current are measured on the output of therespective power distribution feeder. These measurements requireaccuracy on the order of 10 bit digital accuracy (<0.1% full scaleaccurate) when converted from analog signals. In addition, the arc mustbe extinguished within approximately one milli-second. To do so requiresa very fast analog to digital converter, fast digital data manipulationand command execution via the solid state shunt switch.

In the present invention, this feat is accomplished by software runningon the same single chip slave microcontroller used for real time controlof the power switches. The voltage and analog signals are routed throughbuffering circuits directly to the analog inputs of the microcontrollerchip. By using a microcontroller with an on-chip 10 bit accurate analogto digital converter, having a conversion time of approximately 20microseconds per channel, an efficient software code for themicrocontroller, which implements the described algorithm, allows themicrocontroller to quickly manipulate the received converted data todetect the arc and then issue a digital command to the power controlcircuit, instructing the shunt transistor to turn on, thereby shuntingthe arc energy from the arcing node to ground and, hence, extinguishingthe arc.

In the preferred embodiment described herein, all four channels underthe control of a single slave microcontroller can be scanned for arcdetection within the prescribed 1 millisecond period. In systemsrequiring more channels to be scanned within the 1 millisecond, adifferent, faster microprocessor or digital signal processor mustobviously be used to increase data handling capability to continue toimplement the same detection and correction sequence only faster in timeto accommodate the additional channels of power distribution.

The master microcomputer polls the "health" of individual slave units byfirst sending address information and a command for that address. Theslave at that address responds by sending the requested data. Analogsand discretes are sampled. Health is determined continuously in the mainloop and decisions are made as to trip conditions, such as arc detectionand the like, and commands. The slave microcontroller, as example, sendsobtains and sends digital state data on the associated SSPC indicatingwhether the SSPC is on, conducting current, or off, not conductingcurrent; digital health status information, analog voltage and currentdata for each SSPC power output channel.

Reference is next made to FIG. 10 which presents a schematic diagram ofthe external data input output controller card, earlier generallydescribed in FIG. 3. While not necessary for an understanding of theinvention, it is believed that it may be helpful. As earlier describedthis optional card and microcontroller allows signal conditioning andcommunication with additional outside sources as may be desired incertain instances. The input output controller card is for analog anddiscrete data acquisition and the control and issuance of commands toother equipment controlled by discrete electrical signals, such aselectromechanical relays. As illustrated the input output controllercard contains its I/O controller, Analog Mux's, shown to the left forthe analog inputs, power circuitry, appropriate handshake inputs,discrete inputs, analog Mux's, bidirectional discretes, all as labeledand illustrated in the drawings. While the elements and mode ofoperation of the elements of the input output controller card areevident to those skilled in the art, inasmuch as detailed description ofthe elements and operation of that input output controller card are notnecessary to an understanding of the present invention those detailsneed not be further described.

It is appreciated that the serial bus eliminates the large number ofanalog and digital signals being transferred by the backplane prevalentin the prior systems. EMI and attendant corruption of data signals isreduced thereby through increased spacing between the serial bus and thehigh power transmission paths. Through the incorporation of the shadowmicrocontroller, back up power supply and hardwired override thecontroller provides both fail-safe and fail-operate modes of operation.

The power controller offers advantage over corresponding powercontrollers constructed in accordance with the prior parallel busarrangement. As example the back plane wiring is reduced from 900 tracesand 1200 holes to only 150 traces and 200 holes. The local response tosensor data was reduced from a 100 ms latency to a 1 millisecondlatency. Twenty four input output chips were required by the priordesign; the present requires only one. And the power consumption wasreduced from ten watts to only five watts.

The system is easily reconfigured. By including additional connectors onthe backplane and room for additional load cards, additional loads maybe controlled without EMI interference occurring in the backplane.

It is believed that the foregoing description of the preferredembodiments of the invention is sufficient in detail to enable oneskilled in the art to make and use the invention. However, it isexpressly understood that the detail of the elements presented for theforegoing purposes is not intended to limit the scope of the invention,in as much as equivalents to those elements and other modificationsthereof, all of which come within the scope of the invention, becomesapparent to those skilled in the art upon reading this specification.Thus the invention is to be broadly construed within the full scope ofthe appended claims.

What is claimed is:
 1. A modular power controller for selectivelycontrolling the supply of electrical power to a plurality of separateelectrical loads, comprising:master digital microcontroller means,including master program means and memory means containing load commandinformation for each of said electrical loads; serial data bus means;said master digital microcontroller means being located at a firstlocation having a first serial output port connected to said serial databus for selectively issuing load command information in digital serialform onto said serial data bus for each of said plurality of electricalloads; a plurality of load control means, said load control means beingspaced from one another and positioned at other locations spaced fromsaid master controller means; each said load control means beingconnected to said serial data bus for receiving said commandinformation; each of said load control means comprising:slavemicrocomputer means, including slave program means; a plurality ofelectrical load circuits associated with said microcomputer means; saidslave microcomputer means for receiving said load command information inserial form transmitted by said master digital microcontroller means viasaid serial bus and processing said received command information, andsaid slave microcomputer means selectively providing power to respectiveones of said plurality of electrical load circuits based upon theprocessed load command information.
 2. The invention as defined in claim1, wherein said master microcontroller means contains default loadcontrol information for each of said load control means; and whereinsaid master microcontroller means includes: second serial output means,and means for assembling and issuing a default load command informationfor each of said load control means in a serial bit stream via saidsecond serial output means; andwherein each load control means furtherincludes:means for extracting and holding said default load controlinformation from said serial bit stream.
 3. The invention as defined inclaim 2, wherein said means for extracting and holding default loadcontrol information from said serial bit stream comprises shift registermeans; andmeans for connecting said shift register means of all saidload control means into a daisy chain connected to said second serialoutput means of said master digital microcontroller means.
 4. Theinvention as defined in claim 2, further comprising:second serial busmeans; and wherein said means for extracting and holding load controlinformation comprises serial to parallel shift register means, saidshift register means including a register, a serial input, a serialoutput and a parallel output; said second serial bus means being coupledto said second serial output port of said master digital microcontrollermeans and a first of said shift register means for delivering saidserial bit stream to a first shift register means; and daisy chaincircuit means connecting a respective serial output of each of saidshift register means to a respective serial input of the next adjacentshift register means in said plurality to form a daisy chain of shiftregisters.
 5. The invention as defined in claim 1, wherein each of saidload control means includes:shift register means; said shift registermeans including a serial input for receiving digital data input bits, anoverflow serial output for outputting digital data bits, and a paralleloutput for outputting the contents temporarily stored in said shiftregister means, and clock input for receiving clock pulses to shift saidshift register means, whereby digital bits appearing at said input areentered into said register means, bits in said shift register means areserially advanced in position in said shift register means from onestage therein to the next, and digital bits residing in said final stageof said shift register means are advanced out of said serial output atsaid overflow serial output in response to a clock pulse; wherein saidmaster microcontroller means includes:second serial output means; andclocking means for producing clock pulses to clock out a serial digitaldata pattern from said second serial output means, one bit at a time;said master microcontroller means producing a serial bit pattern ofdigital information comprising a plurality of packets of information forregistration of respective packets in corresponding ones of said shiftregister means with only one of said packets containing a coderepresentative of the default load command information sent by saidmaster microcontroller to the load control means containing said shiftregister means; clock bus means for connecting said clocking means incircuit with each of said shift register means to convey clock pulses tosaid clock input of each of said shift register means; first lead meansfor coupling said second serial output means to a shift register meansinput of a first of said plurality of load control means; daisy chainlead means for connecting said shift register output of each of saidload control means, excepting a last one of said shift register means,to a shift register means serial input of one other load control meanson a mutually exclusive basis to interconnect all said shift registermeans in a daisy chain circuit arrangement; wherein digital informationclocked from said second serial output means is paraded into said shiftregisters, and wherein said main microcontroller means clocks out apredetermined parade of digital bits to fill all of said shiftregisters, in response to a predetermined number of clock pulses issuedby said main microcontroller means and wherein said digital bits storedthereby in the shift register of a selected one of said load controlmeans selected by said master microcontroller means, upon cessation ofsaid clock pulses, defines, at the parallel output of said selectedshift register, a unique pattern of bits representative of said defaultload command information issued by said master microcontroller to saidselected load control means via said serial bus.
 6. The invention asdefined in claim 5, wherein said parade of bits from said verificationmeans comprises in number a number equal to the number of shift registermeans multiplied by the number of serial bits that said shift registermeans is capable of registering.
 7. The invention as defined in claim 5wherein each load control means further comprises a plurality ofsemiconductor power switch means for controlling power supplied torespective ones of said electrical load circuits in response to commandsissued by said slave microcomputer means, the modular power controllerfurther comprising:a plurality of prioritizing means, one for each ofsaid semiconductor power switch means; each of said prioritizing meanshaving multiple inputs, with each input being ranked in level ofpriority from highest priority to lowest priority, and having an output;said output of each said prioritizing means being connected to an inputof a respective one of said semiconductor power switch means; means forcoupling the parallel output of said shift register means to the highestpriority input of said prioritizing means in response to a defaultpriority condition; means connecting the output of said slavemicrocontroller means to the lowest priority input of said prioritizingmeans; watchdog circuit means; a plurality of gating means, each of saidplurality of gating means being associated with a corresponding one ofsaid plurality of semiconductor power switch means; said watchdogcircuit means having an input for receiving load commands issued by saidslave microcomputer means and for producing a plurality of digital FALSEoutputs responsive to receiving said load commands and producing aplurality of digital TRUE outputs in the absence of said load commands,said plurality of digital outputs corresponding in number to saidplurality of gating means; means coupling each output of said watchdogcircuit means to a control input of a corresponding one of said gatingmeans; a plurality of monitoring means, one of each of said plurality ofsemiconductor power switch means; each said monitoring means associatedwith each of said semiconductor power switch means for producing anoutput representative of the current conducting state of the associatedsemiconductor power switch means; means coupling the output of each saidmonitoring means to a second input of a corresponding of said gatingmeans; means coupling said output of said gating means to a greaterpriority input of said prioritizing means than said output of said slavemicrocontroller means and lower in priority than said priority input ofsaid shift register means parallel output; said gating means foroutputting the respective input at said second input only in response toa TRUE input at the respective control input, whereby said watchdogcircuit means maintains said semiconductor power switch means in itsexisting conductivity state upon the failure of said slave microcomputermeans, overriding any commands thereafter from said slave microcomputermeans, in the absence of a default condition and whereby saidsemiconductor power switch means is set into the default loadconfiguration in response to a default load condition, irrespective ofthe outputs of either said watchdog circuit means and said slavemicrocontroller means.
 8. The invention as defined in claim 1 whereineach load control means further comprises a plurality of semiconductorpower switch means for controlling power supplied to respective ones ofsaid electrical load circuits in response to commands issued by saidslave microcomputer means, the modular power controller furthercomprising:a plurality of prioritizing means, one for each of saidsemiconductor power switch means; each of said prioritizing means havingmultiple inputs, with each input being ranked in level of priority fromhighest priority to lowest priority, and having an output; said outputof each said prioritizing means being connected to an input of arespective one of said semiconductor power switch means; meansconnecting the output of said slave microcontroller means to the lowestpriority input of said prioritizing means; watchdog circuit means; aplurality of gating means, each of said plurality of gating means beingassociated with a corresponding one of said plurality of semiconductorpower switch means; said watchdog circuit means having an input forpulses issued by said slave microcomputer means and for producing aplurality of digital FALSE outputs responsive to receiving said loadcommands and producing a plurality of digital TRUE outputs in theabsence of said pulses for a predetermined period of time, saidplurality of digital outputs corresponding in number to said pluralityof gating means; means coupling each output of said watchdog circuitmeans to a control input of a corresponding one of said gating means; aplurality of monitoring means, one for each of said plurality ofsemiconductor power switch means; each said monitoring means associatedwith each of said semiconductor power switch means for producing anoutput representative of the current conducting state of the associatedsemiconductor power switch means; means coupling the output of each saidmonitoring means to a second input of a corresponding of said gatingmeans; means coupling said output of said gating means to a greaterpriority input of said prioritizing means than said output of said slavemicrocontroller means; said gating means for outputting the respectiveinput at said second input only in response to a TRUE input at therespective control input, whereby said watchdog circuit means maintainssaid semiconductor power switch means in its existing conductivity stateupon the failure of said slave microcomputer means, overriding anycommands thereafter from said slave microcomputer means.
 9. Theinvention as defined in claim 1, further comprising:arc extinguishingmeans associated with each electrical load circuit; said arcextinguishing means comprising:first semiconductor switch means having acontrol input and an output, said output being connected across saidload circuit, said first semiconductor switch means being normally in anon-conductive state and switchable to an electrically conductive state,responsive to a TRUE input applied to said control input of said firstsemiconductor switch means; current sensor means for monitoring currentflow in said load circuit and providing an output indicative of currentlevel; second semiconductor switch means, having a control input and anoutput, said second semiconductor switch means being normally in anelectrically conductive state and being switchable to an electricallynon-conductive state responsive to a TRUE input applied to said controlinput of said second semiconductor switch means, said secondsemiconductor switch means being connected in series with said loadcircuit; control circuit means for supplying a TRUE input to saidcontrol input of said second semiconductor switch means, responsive tosaid current sensor means output attaining a predetermined interruptlevel; means for inputting said current sensor means output to saidrespective slave microcomputer means, wherein said respective slavemicrocomputer means senses the level of said line current; voltagesensing means for coupling said load circuit to said respective slavemicrocomputer means, wherein said respective slave microcomputer meanssenses the level of said line-voltage; said slave microcomputer meansincluding program means for detecting the simultaneous presence of lowline voltage on said load circuit and a zero line current measured bysaid current sensor means and for providing a TRUE input to said firstsemiconductor switch means, whereby said first semiconductor switchmeans provides a conductive circuit across the lines of said loadcircuit.
 10. The invention as defined in claim 9 furthercomprising:analog to digital converter means for converting currentlevels sensed by said current sensor means and voltage levels sensed bysaid voltage monitoring means to digital form for respective input tosaid slave microcomputer means.
 11. The invention as defined in claim 1wherein each load control means further comprises a plurality ofsemiconductor power switch means for controlling power supplied torespective ones of said electrical load circuits in response to commandsissued by said slave microcomputer means, the modular power controllerfurther comprising:verification means for verifying said load commandinformation received at said load control means prior to selectivelyindividually setting the electrical state of each of said associatedsemiconductor power switch means in accordance with said load controlinformation.
 12. The invention as defined in claim 11, wherein saidmaster digital microcontroller means includes verification serial inputmeans; and wherein said verification means comprises:buffer meanslocated at each load control means, each said buffer means for receivingand holding load command information from the associated slavemicrocontroller means; register means for receiving a copy of said loadcommand information; means for copying said load command informationinto said buffer means; and means for sending said copy of said loadcommand information to said master digital controller means, whereinsaid master digital controller means verifies said load commandinformation; and means for outputting said load command information fromsaid buffer means to said semiconductor power switch means, responsiveto said master digital controller verifying said load commandinformation.
 13. The invention as defined in claim 1 wherein each loadcontrol means further comprises a plurality of semiconductor powerswitch means for controlling power supplied to respective ones of saidelectrical load circuits in response to commands issued by said slavemicrocomputer means,wherein said master digital microcontroller meansincludes a verification serial input, a strobe output and a clockoutput; wherein said slave microcontroller includes a write commandoutput; and wherein each said load control means further includes:shiftregister means; first latch means; second latch means; said first latchmeans having an input coupled to said output of said slavemicrocontroller means for receiving a copy of said load commandinformation and outputting said load control information, responsive toa write command from said slave microcontroller means; said second latchmeans having an output connected to said semiconductor power switchmeans and an input connected to an output of said first latch means forcoupling load command information to said semiconductor power switchmeans, responsive to a strobe signal from said master digital controllermeans; means for loading said shift register means with a copy of saidload command information from said first latch means, responsive to aload signal from said master digital controller means; means in saidslave microcontroller for supplying a write command following output ofsaid load command information, whereby said load command is entered insaid first latch means; means connecting said shift register means ofeach of said load control means in a serial chain to said verificationserial input of said master microcontroller means, wherein a serialoutput of one said shift register means is connected to the serial inputof the next shift register means in said chain, whereby a serial line ofdata containing load command information for each of said load controlmeans is formed in response to said load signal from said master digitalmicrocontroller means; means in said master digital microcontrollermeans for supplying a load command to each of said power control means,whereby said shift register means are loaded with a copy of load commandinformation; means in said master microcontroller means for initiatingsaid clock output to supply clock pulses to each of said shift registermeans, wherein said serial line of data is shifted into said mastermicrocontroller means; said master microcontroller means furtherincluding: means for comparing load command information received viasaid verification serial input means with the load command informationpreviously sent to said slave microcontroller means via said serial databus and, responsive to a match thereof, for providing a strobe output tosaid second latch means, whereby said load command information isentered into said semiconductor power switch means.
 14. In a modularpower controller of the type containing a controller card, a pluralityof load cards and a backplane card in which each of said controllercards and load cards are interconnected in circuit by means of saidbackplane card, wherein said modular power controller selectivelycontrols the supply of electrical power to a plurality of separateelectrical loads, the improvement therein wherein said controller cardissues command information selectively in serial digital form onto saidbackplane card for each of said load cards; and wherein each said loadcard includes a plurality of semiconductor power switches and anembedded microprocessor, said embedded microprocessor for receivingcommand information in serial form transmitted from said controller cardvia said backplane card, for interpreting and processing said receivedcommand information and for selectively controlling the electrical stateof said semiconductor power switches associated therewith responsive tosaid interpreted processed received information, whereby each load cardindividually controls a plurality of electrical load circuits.
 15. In amodular power controller of the type containing a controller card, aplurality of load cards and a backplane card in which each of saidcontroller cards and load cards are interconnected in circuit by meansof said backplane card, wherein said modular power controllerselectively controls the supply of electrical power to a plurality ofseparate electrical loads, the improvement therein wherein saidcontroller card issues command information selectively in serial digitalform onto said backplane card for each of said load cards; and whereineach said load card includes a plurality of semiconductor power switchesand an embedded microprocessor, said embedded microprocessor forreceiving command information in serial form transmitted from saidcontroller card via said backplane card, for interpreting and processingsaid received command information and for selectively controlling theelectrical state of said semiconductor power switches associatedtherewith responsive to said interpreted processed received information,whereby each load card individually controls a plurality of electricalload circuits; and wherein said controller card contains a defaultcommand output for providing default command information; wherein eachsaid load card contains a daisy chain input and a daisy chain outputconnected respectively to said backplane card; and wherein saidbackplane card includes circuit means for connecting said daisy chaininput of a first one of said plurality of said load cards to a verifyoutput of said controller card and for connecting said daisy chain inputof each of said remaining load cards to said daisy chain output of therespective preceding load card in said daisy chain; and wherein eachsaid load card further includes:a plurality of prioritizing means, eachsaid prioritizing means having at least two priority inputs for passingonly the signal at the input having the highest priority, each of saidplurality of prioritizing means being associated with a respective oneof said plurality of semiconductor switch means on said load card;semiconductor registering means for receiving said command informationat said daisy chain input and passing said command information to saiddaisy chain output, wherein said command information is passed to thenext successive load card in said daisy chain, and for outputting saidreceived command information to a first input of each of said pluralityof associated comparison means; each said comparison means having asecond of said inputs coupled to an output of said embeddedmicrocontroller for receiving low level command information from saidmicrocontroller; and wherein each of said plurality of semiconductorswitch means on said respective load card being responsive to a TRUEoutput from an associated one of comparison means for completing anelectrical power transmission circuit.
 16. The invention as defined inclaim 15, wherein said controller card includes:clock means forproviding clock pulses; clock bus means wired between said controllercard and each of said load cards to provide verify clock pulses to eachof said load cards; and wherein said semiconductor verifying meanscomprises:serial to parallel shift register means;said shift registermeans having a serial input connected to said verify input of said loadcard; a clock input connected to said verify clock bus for shifting datainto and serially advancing data through said shift register in responseto clock pulses; a serial output connected to said verify output of saidload card for outputting data bits shifted through said shift registerresponsive to successive clock pulses, and a parallel output foroutputting the contents of said shift register in parallel form; andwherein said parallel output of said shift register means is connectedto said first input of said comparison means.
 17. The invention asdefined in claim 15, wherein said embedded microcontroller on each loadcard further includes means for compiling and transmitting a report ofthe electrical status of said load card in serial form via saidbackplane card to said controller card; and wherein said controller cardincludes means for receiving and assessing said electrical statusinformation.
 18. The invention as defined in claim 17, wherein saidelectrical includes status of electrical arcing.
 19. The invention asdefined in claim 15, further including latch circuit means forpreventing change of state of said semiconductor switch means responsiveto withdrawal of electrical power.
 20. The invention as defined in claim15 wherein said controller card includes microprocessor means, shadowmicroprocessor means, and means for detecting disablement of saidmicroprocessor means, said shadow microprocessor means performingidentical functions to said microprocessor means and providing output toreplace output from said microprocessor means only in the event ofdetection of disablement of said microprocessor means.
 21. The inventionas defined in claim 20, further comprising:first power source means forproviding electrical to said microprocessor means; and back up powersource means for providing alternate electrical power to saidmicroprocessor means only in the event of failure of said first powersupply means.
 22. In a modular solid state power controller of the typecontaining:a panel; said panel containing:first coupling means forcoupling to an external electrical power source, second coupling meansfor coupling electrical power to a plurality of electrical loads andinput coupling means for receiving electrical data from an externalsource; a first circuit board; said first circuit board containing amaster digital microcontroller, said digital microcontroller having aninput coupled to said input coupling means for receiving and processingsaid electrical data; a plurality of slave circuit boards, each saidslave circuit boards containing switching means for controlling the flowof electrical power in a respective plurality of electrical loadcircuits between an on and an off state; a backplane circuit board; saidbackplane circuit board containing a plurality of electrical connectormeans, first electrical transmission paths for interconnecting signalsfrom said master microcontroller and said slave circuit cards and secondelectrical transmission paths for interconnecting electrical powerbetween said respective slave circuit boards and said second couplingmeans of said panel, said second electrical transmission pathscomprising a plurality of individual transmission paths; said panel,first circuit board and said slave circuit board being oriented inspaced parallel relationship and orthogonal to said backplane circuitboard; each of said first circuit board and said slave circuit boardscontaining electrical connector means for mating engagement with amating electrical connector means on said backplane circuit board,wherein said first electrical transmission paths is connected amongstall said circuit boards and wherein said second electrical transmissionpath is connected amongst all said slave circuit boards and said secondcoupling means of said panel; the improvement wherein said powerswitching means comprises semiconductor switch means, said semiconductorswitch means having a control input and being switchable betweenelectrical conducting and non-conducting states in dependence upon acontrol signal applied to said control input; wherein said mastermicrocontroller means includes means for issuing command signals inserial digital form and applying same to said first electricaltransmission path of said backplane circuit board responsive to saiddata information; and wherein each of said slave circuit boards furthercontains slave microcontroller means having an output coupled to saidcontrol input of said semiconductor switch means for receiving saidcommand signals in serial form via said first electrical transmissionpath and processing said command signals to low level command signalsapplied to said output for controlling the electrical state of saidsemiconductor switch means.
 23. The invention as defined in claim 22,wherein said semiconductor switch means comprises a plurality ofindividual semiconductor switches; and wherein said output of said slavemicrocontroller means comprises a plurality of outputs with one outputfor each of said semiconductor switches, whereby said semiconductorswitches are individually controlled by said slave microcontroller. 24.A power controller comprising:master digital microcontroller means,including program means; a plurality of N load control means, each loadcontrol means including a programmed digital slave microcomputer means;and a plurality of Y semiconductor power switches associated with saidprogrammed digital microcomputer means, each of said semiconductor powerswitches being configurable between at least two modes of operation; aserial data bus, said serial data bus coupled between said masterdigital microcontroller means and said N load control means to provide adigital communication path therebetween; each said programmed digitalslave microcomputer means having a communications port connected to saidserial data bus; said master digital microcontroller means containingload configuration information for each of said Y power semiconductorswitches on each of said N load control means and address informationfor each of said N load control means, and having a first serial outputfor outputting addressed load configuration command information indigital serial form onto said serial data bus for communication to arespective addressed digital slave microcomputer in a selected loadcontrol means, whereby each of said N load control means selectivelyreceives load configuration command information from said mastermicrocontroller via said serial bus; said master digital microcontrollermeans further having a second serial output; a plurality of N serial toparallel shift registers, each having a serial input, a serial outputand an inhibit input; each of said shift registers being associated witha corresponding one of said load control means; daisy chain circuitmeans coupling said second serial output port of said master digitalmicrocontroller means and said serial inputs and serial outputs of eachof said N shift registers in a daisy chain, wherein digital bitsoutputted from said second serial output port is inputted into a firstshift register means in said daisy chain and digital bits outputted froma serial output of one shift register means is inputted to the nextshifter register means in said daisy chain; said master microcontrollerincluding program means for selectively assembling packets of loadconfiguration information for each of said N load control means in theform of data bits and assembling the first through Nth packets of databits in reverse serial order to form a stream of digital bits with theNth packet for said Nth shift register means being arranged first insaid stream and said 1st data packet for the 1st shift register means insaid daisy chain arranged last in said stream and outputting said streamof bits from said second serial port, whereby each of said N shiftregister means respectively receives and registers specified loadconfiguration information and outputs the registered load configurationinformation at its respective parallel output; each said load controlmeans, further including:prioritizing gate means having a plurality ofpriority level inputs between at least first and second priority levelsfor outputting only the data present on the higher priority level input;said parallel output of said associated shift register means beingconnected to said first level priority input of said prioritizing gatemeans and load configuration command information from an output of saidassociated slave microcomputer means being connected to said secondlevel priority input of said prioritizing gate means, whereby said Ysemiconductor power switch means is set to the configuration specifiedby the load configuration command information from the higher levelinput.
 25. The invention as defined in claim 24, furthercomprising:selectively operable inhibit switch means for preventingadditional inputs to said serial inputs of each of said shift registermeans to prevent change in load configuration information at therespective parallel output of each of said shift register means.
 26. Theinvention as defined in claim 25, wherein said master microcontrollermeans includes a third output port; means for coupling said third serialinput port to said shift register means output of said Nth shiftregister means; and wherein said master microcontroller includes programmeans for providing a predetermined number of digital bits at saidsecond output of said master microcontroller means to parade loadconfiguration information in said shift register means into said mastermicrocontroller means and for comparing the load configurationinformation in said parade with load configuration information retainedin said master microcontroller means.
 27. A computerized arcextinguishing circuit for an electrical load circuit comprising:arcextinguishing means associated with said electrical load circuit; saidarc extinguishing means comprising:first semiconductor switch meanshaving a control input a nd an output, said output being connectedacross said load circuit, said first semiconductor switch means beingnormally in a non-conductive state and switchable to an electricallyconductive state, responsive to a TRUE input applied to said controlinput of said first semiconductor switch means; current sensor means formonitoring current flow in said load circuit and providing an outputindicative of current level; second semiconductor switch means, having acontrol input and an output, said second semiconductor switch meansbeing normally in an electrically conductive state and being switchableto an electrically non-conductive state responsive to a TRUE inputapplied to said control input of said second semiconductor switch means,said second semiconductor switch means being connected in series withsaid load circuit; control circuit means for supplying a TRUE input tosaid control input of said second semiconductor switch means, responsiveto said current sensor means output attaining a predetermined interruptlevel; microcomputer means, including program means for detecting thesimultaneous presence of a low line voltage on said load circuit and azero line current measured by said current sensor means and forproviding a TRUE input to said first semiconductor switch means, wherebysaid first semiconductor switch means provides a conductive circuitacross the lines of said load circuit; means for inputting said currentsensor means output to said microcomputer means, wherein saidmicrocomputer means senses the level of said line current; and voltagesensing means for coupling said load circuit to said microcomputermeans, wherein said microcomputer means senses the level of said linevoltage.
 28. The invention as defined in claim 27, furthercomprising:analog to digital converter means for converting currentlevels sensed by said current sensor means and voltage levels sensed bysaid voltage monitoring means to digital form for respective input tosaid microcomputer means.